This invention relates to high frequency semiconductor devices and, more particularly, to an electrode structure with low parasitic capacitance and a method for fabricating low capacitance electrodes in a semiconductor device while avoiding the requirement for precision mask alignment.
Semiconductor devices designed for high frequency operation require electrodes having extremely small dimensions and must be fabricated under extremely tight dimensional control to minimize stray capacitance and series resistance. Devices designed for operation at or above one gigahertz utilize electrode widths of one or two microns and electrode separations of a few microns. Photolithographic alignment and mask to mask registration, therefore, requires a precision of a few tenths of a micron. Such requirements make processing of high frequency semiconductor devices costly and difficult.
One example of a device requiring precision alignment and mask to mask registration is the static induction transistor, a field effect device which exhibits excellent high power and high frequency capabilities. The static induction transistor (SIT) typically utilizes a vertical geometry. Source and drain contacts are placed on opposite sides of a thin, high-resistivity layer of one conductivity type. Gate regions of the opposite conductivity type are diffused into the high resistivity layer on opposite sides of the source. Gate and source widths are typically 1.5 microns while the gate to source spacing is typically 5 microns. A slight mask misalignment can result in short-circuited semiconductor devices or can degrade device performance. Furthermore, the parasitic capacitance associated with metallic contact overlap degrades device performance. It is, therefore, desirable to provide an electrode structure in which the parasitic capacitance associated with metallic contact window overlap is reduced and to provide a method for fabricating low capacitance electrodes in semiconductor devices while avoiding the requirement for precision mask alignment and mask to mask registration.